1. Field of the Invention
This invention relates to a clock generator, and more particularly to a clock generator which generates a clock signal of further high frequency required for a digital signal processor or the like operating at high speed.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of the conventional 4-phase non-overlap clock generator and FIG. 2 is a timing chart thereof. The clock generating circuit, whose structure is shown in FIG. 1, is similar in fundamental structure and operation to a circuit disclosed in the "Handbook of Microcircuit Design and Application" chapter 9, pages 9-3 to 9-4, written by David F. Atout and published by McGRAW-HILL Book Company.
In FIG. 1, a reference numeral 1 designates a 1/2 frequency divider. The 1/2 frequency divider 1 generates signals A and B of external clock ECLK inputted from the exterior divided into 1/2, that is, of frequency two times larger than the external clock ECLK.
The 1/2 frequency divider 1 comprises AND gates 2 and 3, NOR gates 4 and 5, OR gates 6 and 7 and NAND gates 8 and 9.
Concretely, the external clock ECLK is introduced into the AND gates 2 and 3 and OR gate 6, the output of AND gate 2 being introduced in the NOR gate 4, and the output of AND gate 3 being introduced in the NOR gate 5. The output D of NOR gate 4 is introduced in the NOR gate 5 and OR gate 6, the output of NOR gate 5 being introduced into the NOR gate 4 and OR gate 7.
Meanwhile, the output of OR gate 6 is given into the NAND gate 8, the output B of the NAND gate 8 being introduced into the AND gate 3 and NAND gate 9 and also to the exterior of 1/2 frequency divider 1. Furthermore, the output of OR gate 7 is introduced into the NAND gate 9, the output thereof being introduced in the AND gate 2 and NAND gate 8 and also to the exterior of the 1/2 frequency divider 1.
Reference numeral 10 designates an AND gate outputting a first clock .phi..sub.1, by taking a logical product of the output A of the NAND gate 9 and external clock ECLK.
Reference numeral 11 designates an AND gate outputting a second clock .phi..sub.2 by taking a logical product of the output B of NAND gate 8 and external clock ECLK.
Reference numeral 12 designates an AND gate outputting a third clock .phi..sub.3 by taking a logical product of the output B of the NAND gate 8 and external clock ECLK.
Reference numeral 13 designates an AND gate outputting a fourth clock .phi..sub.4 by taking a logical product of the output A of NAND gate 9 and external clock EDLK.
The first clock .phi..sub.1, the output of AND gate 10 is introduced into the AND gate 11 through an inverter 14, the second clock .phi..sub.2, the output of AND gate 11 into the AND gate 12 through an inverter 15, the third clock .phi..sub.3, the output of AND gate 12 into the AND gate 13 through an inverter 16, and the fourth clock .phi..sub.4, the output of AND gate 13 into the AND gate 10 through an inverter 17.
Such conventional pulse generating circuit operates as shown in the timing chart in FIG. 2 and as follows:
When the 1/2 frequency divider 1 is given the external clock ECLK, the signal A is turned to a low level in synchronism with the trailing edge of external clock ECLK and to a high level in synchronism with the next trailing edge of the external clock ECLK.
The signal B is turned to a low level in synchronism with the trailing edge of external clock ECLK and to a high level in synchronism with the next trailing edge of external clock ECLK.
The signal C is turned from the high level to the low level in synchronism with the leading edge of external clock ECLK and from the low level to the high level in synchronism with the next leading edge of external clock ECLK.
The signal D is turned from the high level to the low level in synchronism with the leading edge of external clock ECLK and from the low level to the high level in synchronism with the next leading edge of external clock ECLK.
The first clock .phi..sub.1, is the output of the AND gate 10 into which the external clock ECLK, signal A and an inverted signal fo the fourth clock .phi..sub.4 being the output of inverter 17 are introduced. Accordingly, since the first clock .phi..sub.1, is inhibited from being at a high level for the period of time when the fourth clock .phi..sub.4 is at a high level, the first clock .phi..sub.1, is prevented from overlapping with the fourth clock .phi..sub.4.
The second clock .phi..sub.2 is the output of AND gate 11 into which an inverted signal of external clock ECLK, the signal B and an inverted signal of the first clock .phi..sub.1 being the output of the inverter 14 are introduced. Accordingly, since the second clock .phi..sub.2 is inhibited from being at a high level for the period of time when the first clock .phi..sub.1 is at a high level, the second clock .phi..sub.2 is prevented from overlapping with the first clock .phi..sub.1.
The third clock .phi..sub.3 is the output of AND gate 12 into which the external clock ECLK, signal B and an inverted signal of the second clock .phi..sub.2 being the output of the inverter 15 are introduced. Accordingly, since the third clock .phi..sub.3 is inhibited from being a high level for the period of time when the second clock .phi..sub.2 is at a high level, the third clock .phi..sub.3 is prevented from overlapping with the second clock .phi..sub.2.
Furthermore, the fourth clock .phi..sub.4 is the output of AND gate 13 into which an inverted signal of external clock ECLK, the signal A and an inverted signal of the third clock .phi..sub.3 being the output of the inverter 16 are introduced. Accordingly, since the fourth clock .phi..sub.4 is inhibited from being at a high level for the period of time when the third clock .phi..sub.3 is at a high level, the fourth clock .phi..sub.4 is prevented from overlapping with the third clock .phi..sub.3.
Thus, the first clock .phi..sub.1, through the fourth clock .phi..sub.4 are non-overlap 4-phase clocks.
The above conventional clock generator has various problems as follows:
A circuit scale is relatively larger and the frequency of generated clock cannot desirably be changed.
The clock used withint he processor is required of further high frequency, as the digital signal processor has recently been improved in performance, but it is difficult from restriction of a crystal oscillator or the like for being given the external clock that the external clock of a duty ratio of 50% or more is obtained in a further higher frequency zone.
In the above-mentioned conventional clock generator, however, the external clock ECLK is given at the four AND gates 10 through 13, whereby waveforms of the first clock .phi..sub.1 to fourth clocks .phi..sub.4 depend on the waveform of external clock ECLK. Therefore, it is difficult to obtain the clock to meet conditions of spec needful to the processor such as, for example, the frequency and non-overlap clock.